Taiwan Semiconductor Manufacturing Company (TSM / 2330.TW)

6 September 2026. Built from ten Form 20-F annual reports (FY2016–FY2025, latest filed 16 April 2026) and 434 Form 6-K filings held in the research folder, supplemented by TSMC’s Q1 and Q2 2026 primary investor disclosures and by independent industry sources — TrendForce, Counterpoint, SIA, WSTS, SEMI, IDC — and competitors’ own reporting. This is not a valuation and not a recommendation.

1 · Executive snapshot

2 · What the company does

Designing a chip and manufacturing one are different businesses requiring different assets. A designer needs a few hundred engineers and software licences. A manufacturer needs a factory costing tens of billions of dollars, a decade of process research, and enough volume across many customers to keep that factory full. TSMC exists because those two activities separated. It builds the factory and sells access to it, so Apple, Nvidia, AMD, Qualcomm and Broadcom never have to.

A wafer is a polished silicon disc roughly 300mm across. TSMC receives the customer’s design, translates it into photomasks, and runs the wafer through several hundred process steps that build transistors and their wiring layer by layer. A single wafer takes roughly three months to cross a leading-edge fab and emerges carrying anywhere from a few dozen to several thousand identical chips. The customer is billed for the wafer, not for the working chips on it — which is why yield is the customer’s problem as much as TSMC’s, and why a foundry with better yield can charge more per wafer and still be cheaper per working chip.

Tracing one wafer to cash: the customer commits capacity months ahead, sometimes with prepayments — NT$189.9bn of temporary receipts sat on the FY2025 balance sheet. The wafer is processed, tested, often packaged, then billed and collected in an average of 29 days (Q2 2026). Cash arrives quickly. What arrived years earlier was the capital: the equipment that processed the wafer is depreciated over five years, a life unchanged in every filing across the decade.

Price per wafer is set almost entirely by which node runs it. FY2025 wafer revenue split 24% at 3nm, 36% at 5nm, 14% at 7nm, 7% at 16nm and 7% at 28nm — everything at 7nm and below reaching 74% of wafer revenue, up from 58% in FY2023. By Q2 2026 that aggregate was 77%, with 2nm broken out for the first time at 3%.

Packaging has changed character. It was a low-value back-end step, reclassified out of wafer revenue in 2017 (which is why the wafer share of revenue appears to fall from ~96% to ~89% that year without anything real happening). Advanced packaging — CoWoS, SoIC, InFO — is now a bottleneck rather than a commodity, taking 10–20% of the 2026 capital budget alongside testing and mask making. TSMC discloses neither its capacity nor its revenue contribution (unknown).

3 · Industry, competitive position and moat

The foundry industry exists because the cost of a leading-edge fab rose faster than any single designer’s volume. Independent Business Strategies estimated a 50,000-wafer-per-month 2nm fab at roughly US$28bn against about US$20bn at 3nm (a dated 2023 figure; no more recent independent estimate was found). SEMI projects US$133bn of 300mm fab equipment spending in 2026, rising to US$151bn in 2027. At that scale only a manufacturer aggregating demand from hundreds of designers keeps a fab full — and only a full fab earns a return.

The industry is extraordinarily concentrated and became more so through 2025. TrendForce puts full-year 2025 top-ten foundry revenue at US$169.5bn, with TSMC at US$122.5bn and 69.9% share, Samsung Foundry second at 7.2% on revenue that fell 3.9%, and SMIC third at 5.3%. Counterpoint reads TSMC at 73% in Q2 2026, and above 86% of foundry share at 5nm and below — though that figure is anchored on smartphone SoCs, and a clean all-segment leading-edge split by vendor could not be sourced (unknown).

Where the profit pool sits

Ranking the value chain by most recent reported operating margin makes the structure legible. The instructive comparison is not TSMC against Nvidia — it is TSMC against the other foundries, running the same business model in the same quarter.

ASML is omitted from this column because it guides on gross margin: 54.0% in Q2 2026 against 54–56% full-year guidance. TSMC’s 60.3% against GlobalFoundries’ 9.7% is not a foundry rent — it is a leading-edge scarcity rent that one foundry currently collects.

Which barriers actually bind

Several barriers are merely expensive, and money solves them. Japan funded Rapidus with JPY 267.6bn from the state and 32 private companies toward 2nm production in 2027; the United States took a 9.9% equity stake in Intel for US$8.9bn. EUV tool access is binding but purchasable — ASML is raising Low-NA capacity 30% for 2027 and shipping roughly 65 units in 2026. The exception is China, where EUV is unavailable at any price, which is why SMIC remains capped at 7nm with a reported sub-20% yield on a 5nm-class pilot line.

Two barriers money does not solve. The first is yield learning. Samsung’s 2nm yield was reported by Korean media at roughly 55% against TSMC’s 80–90% (April 2026), below the level analysts put at the threshold of profitability; TrendForce reported 55–60% in November 2025, and a February 2026 trade claim of 70% remains unconfirmed. Samsung has spent at scale for a decade and its foundry share still fell in 2025. Yield is accumulated defect-and-process learning against real production volume — and volume is exactly what a challenger cannot get until its yield is good. The second is customer qualification. Intel has 18A in production, a sovereign shareholder, and High-NA EUV before anyone else — and as of January 2026 had two prospective 14A customers and zero committed, with decisions running into 2027 and volume production not before 2028. A design win is a two-to-four-year commitment made against a yield history the challenger does not yet have.

TSMC’s specific position

What would be hardest to reproduce is not any single asset but the compounding loop between them. FY2025 R&D of NT$246.4bn was funded out of NT$2,275.0bn of operating cash flow, so process development is self-financing rather than a call on the balance sheet. That research produces the node that wins the design, the design brings the volume, the volume produces the yield data, and the yield funds the next node. A challenger must enter this loop at its weakest point and fund the gap from elsewhere — which is precisely what Intel Foundry’s US$2.1bn quarterly operating loss represents.

A third asset emerged more recently: advanced packaging is now a second chokepoint alongside the transistor. TrendForce puts TSMC CoWoS capacity at 120,000–140,000 wafers per month in 2026 plus 50,000–60,000 from OSAT partners, with the supply–demand gap narrowing from roughly 20% to 10% by end-2026 and capacity rising a further 60% in 2027. CoWoS wafer ASPs are reported approaching 7nm levels. Controlling both the transistor and the package is materially stronger than controlling either alone.

What could weaken it, in order of speed. Samsung’s 2nm yield could be independently confirmed above the profitability threshold, giving customers a second source — Tesla has already committed US$16.5bn to Samsung’s Taylor, Texas fab. Intel could convert a 14A prospect into a signed commitment; a preliminary, unsigned Apple–Intel arrangement for entry-level M-series parts was reported in May 2026. And TSMC’s own overseas expansion mechanically weakens the cluster advantage it depends on.

The outside evidence answers what kind of company wins here, and it is not the best-capitalised one. Samsung has memory profits, Intel a sovereign shareholder, Rapidus has Tokyo; none has converted capital into leading-edge share. What separates the winner is yield at volume and the customer trust that yield history buys. TSMC is that kind of company — which is also the warning, because the position is defended by an operating record rather than by a legal or physical barrier.

4 · Growth engine

All of TSMC’s growth over the past decade is organic. A review of all ten annual reports found no material acquisition in FY2016–FY2025. Goodwill has been effectively frozen for nine years — NT$6,105m in 2015, NT$5,791.8m of cost basis at end-2024 — and the only movement is attributed to exchange rates. JASM in Japan (2021) and ESMC in Germany (2023) were established, not acquired: TSMC is the controlling founder and Sony, DENSO, Bosch, Infineon and NXP bought minority stakes into TSMC’s vehicles. That is inbound minority capital, not outbound M&A. Reported growth and organic growth are the same number.

Revenue per wafer and the growth shares are inferred from reported revenue and shipments; shares are computed on a logarithmic basis. Packaging and testing revenue was reclassified out of wafer revenue in 2017, so FY2016 sits on a marginally different basis; direction and magnitude are unaffected. TSMC has never disclosed an absolute selling price per wafer (unknown). The FY2022–FY2024 stretch makes the point starkly: shipments fell 15% while revenue rose 28%.

Drivers, ranked

TSMC guided full-year 2026 revenue growth to “slightly above 40% year over year in US dollar terms” on the Q2 2026 call, raised from above 30% three months earlier. Monthly revenue supports it: July 2026 net revenue of NT$467.6bn was up 44.7% year over year, the fastest print in the series.

5 · Margin, cash and capital allocation

The margin structure follows from owning the factories. In TSMC’s own words, “because we own most of our manufacturing capacities, a significant portion of our operating costs is fixed. In general, these costs do not decline when customer demand or our capacity utilisation rates drop.” Depreciation and amortisation of NT$688.1bn in FY2025 was 18% of revenue and is largely insensitive to volume. Operating leverage therefore runs hard in both directions: gross margin was 46.0% in FY2019 and 67.7% in Q2 2026 on a cost base that changes far more slowly than revenue.

Management attributes the FY2025 improvement to 59.9% from 56.1% to “higher capacity utilisation and cost improvement, partially offset by unfavourable foreign exchange rate.” Currency is first-order, not a footnote: TSMC quantifies that every 1% depreciation of the US dollar against the New Taiwan dollar costs approximately 0.3 percentage points of operating margin, because substantially all sales are in US dollars while a large part of the cost base is not.

Operating expenses fell from 11.8% of revenue in FY2023 to 9.1% in FY2025, but this is denominator arithmetic rather than restraint. R&D rose 20.7% in FY2025 to NT$246.4bn, directed at 10-, 14- and 16-angstrom research; it simply grew more slowly than a 31.6% revenue increase.

Comparability: packaging and testing revenue was reclassified out of wafer revenue in 2017, so FY2016 revenue per wafer sits on a marginally different basis. TSMC redefined “advanced technologies” twice over this period (28nm-and-below through FY2018, 16nm-and-below in FY2019–FY2020, 7nm-and-below thereafter), so that ratio is not continuous and is excluded here. IFRS 16 was adopted in 2019. Headline revenue, gross profit, operating income and net income cross-check cleanly across filings with no restatement.

The table shows a business that got more capital-hungry through the 5nm and 3nm build-out and is now, briefly, growing faster than its capital budget. That reversal is unlikely to persist: TSMC raised its FY2026 capital budget to US$60–64bn on the Q2 2026 call, from the US$52–56bn stated in the FY2025 20-F. Against guided revenue growth slightly above 40%, capital intensity rises again in 2026 — and the depreciation from that spending arrives over the following five years.

Cash conversion is unusually clean for a capital-intensive manufacturer. FY2025 operating cash flow of NT$2,275.0bn against net income of NT$1,697.6bn reflects the large non-cash depreciation charge; capex of NT$1,272.4bn leaves roughly NT$1,002.6bn of free cash flow (inferred). Working capital is not a drag: receivables ran at 29 days and inventory at 87 days in Q2 2026, and customers advance cash. The balance sheet carries net cash — NT$3,068.6bn of cash and securities at end-FY2025 against NT$1,033.0bn of long-term debt, rising to about US$110bn by Q2 2026.

The ranking tells you how management thinks, and two constraints shape it. Allocation is overwhelmingly reinvestment, and the dividend has become a genuine second claim — up 55.6% over six quarters, reaching NT$181.5bn for Q1 2026. Buybacks are effectively unavailable: the ROC Company Act restricts repurchases and the CHIPS Act funding agreement adds a five-year restriction. Government grants are material and easy to overlook — NT$76.3bn received in FY2025 from the United States, Germany, Japan and China, roughly 6% of that year’s capital expenditure.

Post-dating the reported figures: the FY2026 capital budget was raised to US$60–64bn (70–80% to advanced process, 10–20% to packaging, testing and masks); in August 2026 TSMC signed a binding agreement with Sony to establish an advanced image-sensor venture in Kumamoto with production from 2029, Sony contributing roughly JPY 465bn and consolidating it, TSMC roughly JPY 282bn phased by demand; and TSMC Arizona’s board resolved a capital increase of up to US$20bn from the parent in May 2026. None of these appear in the FY2025 figures.

6 · Cyclicality, constraints and what to monitor

TSMC is at, or above, its own prior cyclical peak on every dimension that matters. Gross margin of 67.7% in Q2 2026 exceeds the previous decade peak of 59.6% in FY2022 and sits 21.7 points above the FY2019 trough of 46.0%. Revenue per wafer is an all-time high at 2.57 times the FY2016 level. Wafer shipments of 15,022 thousand in FY2025 only marginally approached the FY2022 record of 15,253 thousand — volume is near, not above, prior peak. A record margin at a peak and a record margin at a trough are opposite facts, and this is unambiguously the former.

What makes 2026 unusual is that there is no single semiconductor cycle. Three run in different directions at once, and TSMC touches all three.

In nine years HPC and Smartphone have exactly swapped places. Geographic concentration moved the same way: North American customers were 68% of revenue in FY2023 and 78% in Q2 2026.

The downside mechanism

A downturn arrives through fixed costs meeting a five-year depreciation schedule. TSMC will spend US$60–64bn in 2026, most of it on equipment depreciated over five years. That charge lands regardless of utilisation. If accelerator orders pause — and the demand behind them is the capital budget of roughly five buyers, not a diversified end market — revenue falls against a cost base that had just stepped up. FY2019 is the template: revenue grew 3.6% while gross margin fell 2.3 points and operating margin fell 2.4 points, because the fixed base had been built for a volume that did not arrive.

Two near-term headwinds are already disclosed and are not cyclical. TSMC guides overseas-fab dilution of “2% to 3% in the early stages” widening “to 3% to 4% in the latter stages,” plus roughly 3–4 points of dilution in the second half of 2026 from the steep N2 ramp. Against a stated long-term expectation of “56% and higher through the cycle,” the Q2 2026 result of 67.7% carries about eleven points of cushion — some of which management has already said it intends to spend.

Physical constraints are real but so far modest: a Q1 2025 earthquake cost NT$5.3bn net of insurance, following NT$3bn in Q2 2024. Utility costs are flagged qualitatively with no quantified impact (unknown). TSMC no longer discloses capacity utilisation; the last published figure was 94% in the FY2020 20-F, and that disclosure was withdrawn rather than merely absent.

7 · Risks, unknowns and questions for deeper work

Cyclicality is covered above. What follows is what cyclicality does not capture, ordered by how badly each would compound with the others.

• Customer concentration is tightening at the point of maximum operating leverage. The ten largest customers were 78% of FY2025 revenue, up from 70% two years earlier; the largest was 19% and the second 17%, so two customers are 36% of the company. HPC reached 66% of revenue in Q2 2026. TSMC names the mechanism itself: system companies designing their own semiconductors mean “shifting business models could lead to significant variations in our sales if the growth of their products and services, particularly in the AI sector, is volatile or not sustainable.” A single hyperscaler moving an accelerator programme in-house, or pausing one, removes wafer volume the fixed cost base cannot follow.
• Geographic concentration cannot be diversified away on any relevant timescale. Nine of sixteen fabs plus headquarters and process R&D sit in three Taiwanese science parks. The mitigation — Arizona, Kumamoto, Dresden — takes a decade and arrives at a worse cost structure, and Taiwan’s own policy may cap what technology can leave.
• Export-control liability is structural, not procedural. TSMC states its position in the supply chain “inherently limits our visibility into the downstream use or user of final products,” and disclosed that in October 2024 it notified US and Taiwan authorities that a customer chip it manufactured “might have been diverted to a restricted entity.” A foundry cannot verify end use it never sees, so this exposure recurs with every customer rather than resolving once.
• Overseas margin dilution is permanent rather than transitional. Management guides 2–3 points early, widening to 3–4 later. The widening is the tell: as Arizona scales from one fab to three, Japan from one to two, and Dresden comes online, the higher-cost base grows as a share of the whole. This is not a ramp cost that amortises away.
• Government support carries conditions that constrain capital allocation. Against NT$76.3bn of FY2025 grants, up to US$6.6bn of CHIPS direct funding, up to US$5bn of US loans and up to EUR5bn of German state aid, TSMC guarantees TSMC Arizona’s obligations to the Commerce Department, accepted a five-year buyback restriction, and flags “non-receipt, delay and potential clawbacks” in its own risk factors. The subsidy is real; so is the loss of freedom.
• Antitrust and political scrutiny scale with success. TSMC writes that “with our success in the foundry business and the increasing criticism on the concentration of the semiconductor industry and sometimes directly on us, we are subject to heightened risks of antitrust investigations.” At 70%-plus of foundry revenue this is slow-moving but one-directional.
• A live ITC patent action could reach exclusion orders. Longitude Licensing and Marlin Semiconductor filed complaints in February 2025 alleging that TSMC and its customers infringe five US patents; the ITC instituted an investigation on 21 March 2025 and the parallel Texas case is stayed. TSMC states the outcome cannot be determined and no reliable estimate of liability can be made. The ITC’s remedy is import exclusion, which reaches customers rather than only damages.

What the sources could not answer

• TSMC has never disclosed an absolute selling price or revenue per wafer — every such figure here is inferred from reported revenue and shipments.
• Capacity utilisation is no longer disclosed; the last figure was 94% in the FY2020 20-F.
• No CoWoS or advanced-packaging capacity, revenue contribution, or dedicated capital allocation is disclosed. Everything on packaging capacity above comes from TrendForce, not from TSMC.
• Total committed investment in Arizona and JASM does not appear in the FY2025 20-F; the widely cited US$165bn and US$265bn Arizona figures could not be traced to a TSMC filing.
• The operative state of Taiwan’s N-1 overseas technology rule could not be established — three sources conflict, none newer than April 2025. It determines whether an overseas fab can ever run the leading node.
• A16 timing is contradictory: TSMC said volume production was on track for the second half of 2026 on its Q4 2025 call, while trade press from the April 2026 symposium put the ramp in 2027. TSMC addressed A16 on neither the Q1 nor Q2 2026 call.
• Samsung Foundry’s standalone profitability is not disclosed by Samsung, and no all-segment leading-edge share split by vendor could be sourced.
• The research folder contains no quarterly earnings release after Q1 2020; all Q1 and Q2 2026 figures here come from TSMC’s investor relations site rather than the archive.

Three questions before forming a thesis. How much of HPC revenue is training capacity built ahead of monetised demand — answerable only from the hyperscalers’ own disclosures. What gross margin looks like at trough utilisation with FY2026 capex fully in the depreciation base — a question the 56%-and-higher statement answers only in management’s words. And whether the Taiwan concentration is priced as a risk or as a certainty.

8 · Investor takeaways

• What this business really is: a toll on the leading edge of transistor manufacturing, collected one wafer at a time, from customers who have no qualified alternative at 2nm.
• The economic engine: revenue per wafer, not wafers. Volume grew 1.56× over the decade while price and mix grew 2.57× — and that mix runs through a largely fixed cost base.
• The main growth lever: AI and high-performance computing, now 66% of quarterly revenue, resting on the capital budgets of roughly five buyers.
• What could break the story: not a competitor arriving, but the same fixed-cost leverage running backwards — US$60–64bn of capex depreciated over five years, meeting a pause in accelerator orders. Concentration in two customers and one island compounds it.
• What to monitor: gross margin against the 56%-and-higher through-cycle statement, the 2nm share of wafer revenue, and hyperscaler capital expenditure guidance — the last of which moves first.